1. Field of the Invention
The present invention relates generally to amplifier circuits, and particularly to the improvement of an amplifier circuit of a current mirror type. The present invention has particular applicability to semiconductor memory devices, preferably dynamic random access memory devices (DRAMs).
2. Description of the Background Art
Recently, in advancing high integration of a semiconductor integrated circuit device, reduction in power consumption is desired. Higher speed operation is also desired in a semiconductor integrated circuit device. Generally, a semiconductor integrated circuit device, such as a semiconductor memory, includes an amplifier circuit. Low power consumption and high speed operation, therefore, are desired also in an amplifier circuit formed on the semiconductor substrate.
Although the present invention is generally applicable to an amplifier circuit provided in a semiconductor integrated circuit device, the example in which the present invention is applied to a dynamic random access memory (hereinafter referred to as "DRAM") will be described in the following.
FIG. 6 is a block diagram of a conventional DRAM. Referring to FIG. 6, a DRAM 100 includes a memory cell array 85 including a multiplicity of memory cells, an address buffer 81 receiving externally applied address signals A0 to An, a row decoder 82 and a column decoder 83 responsive to the received address signals for designating a row and a column in memory cell array 85, respectively, and a sense amplifier 84 for amplifying a data signal read from the memory cell. Input data Di is applied through a data input circuit 86. Output data Do is provided through a data output circuit 87.
DRAM 100 further includes a CAS input buffer 91 receiving an externally applied column address strobe signal /CAS, an RAS input buffer 92 receiving an externally applied row address strobe signal /RAS, and a clock generator 88 generating clock signal for controlling various circuits in DRAM 100.
In data write operation, the input data Di to be stored is applied to data input circuit 86, and a signal amplified by circuit 86 is applied to a switching circuit (Y gate circuit), not shown. Column decoder 83 selects one column in memory cell array 85 in response to a column address signal, so that a data signal is applied to one bit line (not shown). Row decoder 82 activates one word line (not shown) in response to a row address signal. The data signal is then written in the memory cell (not shown) selected by row decoder 82 and column decoder 83.
In data read operation, a stored data signal is supplied from a memory cell connected to a word line activated by row decoder 82 to a bit line (not shown). The data signal on each bit line is amplified by sense amplifier 84, and thereafter one amplified signal selected by column decoder 83 is applied to data output circuit 87. Data output circuit 87, which has the circuit structure shown in FIG. 7, amplifies the applied data signal to provide output data Do.
FIG. 7 is block diagram of data output circuit 87 shown in FIG. 6. Referring to FIG. 7, data output circuit 87 includes a preamplifier circuit 61 amplifying complementary input signals VI and /VI, a main amplifier circuit 62 amplifying an output signal VO from preamplifier circuit 61, and an output buffer circuit 63 providing output data Do to the outside. Preamplifier circuit 61 is activated in response to a preamplifier activation signal PAE applied from clock generator 88 shown in FIG. 6.
FIG. 8 is a schematic diagram of an amplifier circuit provided in preamplifier circuit 61 shown in FIG. 7. Referring to FIG. 8, amplifier circuit 40 of a current mirror type includes PMOS transistors 1 and 3 constituting a current mirror circuit, NMOS transistors 4 and 2 respectively operated in response to complementary input signals VI and/VI, an NMOS transistor 7 for controlling activation, and a PMOS transistor 10 and an NMOS transistor 11 constituting a transmission gate for equalization.
In operation, preamplifier circuit 40 is activated when the preamplifier activation signal PAE at a high level is applied. That is, transistor 7 is turned on, and transistors 10 and 11 are turned off. When the input signal VI at a low level is applied, transistors 1, 3 and 4 are turned off, while transistor 2 is turned on in response to the input signal/VI at a high level. Consequently, an output signal VO at a low level is provided through an output node NO.
When the input signal VI at a high level is applied, transistor 4 is initially turned on. Since transistor 4 is rendered conductive, the gate voltages of transistors 1 and 3 are reduced towards a ground potential. As a result, transistor 1 is turned on, so that the output signal VO at a high level is provided through output node NO.
In the inactive period, the preamplifier activation signal PAE at a low level is applied. In response to the signal PAE, transistor 7 is turned off, while transistors 10 and 11 are turned on. Since transistors 10 and 11 are rendered conductive, the potentials of two nodes NO and N1 are equalized.
As has already been described, when the input signal VI at a high level is applied, transistor 4 is turned on, and transistors 1 and 3 are also rendered conductive. In this case, therefore, a feed through current I' shown in FIG. 8 flows from a power supply potential Vcc towards the ground potential. Unnecessary current consumption increases because of the existence of the feedthrough current I'. In addition, since the current I' flows through transistors 4 and 7, the potential of node N1 is raised. Accordingly, the gate voltages of transistors 1 and 3 are raised, so that transistor 1 requires long time for being conductive sufficiently.
Specifically, as shown in the timing chart of FIG. 2, the feedthrough current I' is conducted after the time t3, so that the voltage level of an output signal VO' is gradually raised after once falling from the equalize level. Accordingly, the output signal VO' requires a time period .DELTA.T1 for attaining a desired high level at the time t5, which prevents fast amplifying operation.